1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a node contact.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a memory circuit that is most often used in computers and electronic products. Due to the development of the industry, there is a correspondingly greater need for high-capacity DRAM.
In a memory cell of a DRAM, a node contact is used to connect a capacitor and a transistor. The steps of forming the node contact include etching a dielectric layer on a substrate to form a node contact opening that exposes a part of the substrate, and filling the node contact opening with a conductive layer to form a conductive plug. In order to prevent electrical connection between the conductive plug and bit lines, the width of the conductive plug must be shorter than the distance between the bit lines. In this manner, a reserved tolerance window is obtained. When the node contact opening is patterned, the tolerance of the step needs to be within the range of the tolerance window so as to prevent the conductive plug from making contact with the bit lines. However, as the integration of semiconductor devices increases, the linewidth of the semiconductor devices is decreased. The limitation of the photolithography and etching process prevents the size of node contact opening from being further reduced. In a semiconductor fabrication process with a linewidth lower than 0.2 micrometers, the range of the tolerance window is especially insufficient when forming the node contact opening by the conventional method. This, in turn, causes the contact plug to make contact with the bit line and leads to shorts in devices.
There are two conventional methods to solve the above-described problems. The first method is to form an etching stop layer on the bit lines. During the step of etching the node contact opening, the etching stop layer prevents the bit lines from being etched. However, the method for forming the node contact opening is complicated and easily degrades the product quality. Thus, this method does not benefit the formation of the node contact opening.
Another method solves the problem by adjusting the etching parameters to form a node contact opening. The width of the node contact opening gradually decreases from the top to the bottom. Because the width of the node contact opening gradually decreases from the top to the bottom, the width of the node contact opening between the bit lines is shorter than the width at the surface of the dielectric layer. An electrical connection between the conductive plug and the bit lines does not occur. However, the increase in the width of the reserved tolerance window by this method is limited. The conductive plug still easily makes contact with the bit lines. The quality of the semiconductor devices formed by this method is still poor.
FIG. 1 is a schematic, cross-sectional view of a portion of a semiconductor device showing a conventional node contact.
Referring to FIG. 1, a substrate 100 including a gate 110, a dielectric layer 102, a bit line 106, and a dielectric layer 104 is provided. The dielectric layers 102 and 104 are patterned. A trapezoidally cross-sectioned opening 112 is formed to expose a part of the substrate 100. The width of the trapezoidally cross-sectioned opening 112 gradually decreases from the top to the bottom, which gives the profile of the opening 112 its trapezoidal shape. A conductive plug 114 is formed to fill the trapezoidally cross-sectioned opening 112 and cover a portion of the dielectric layer 104, so as to form a node contact. The node contact formed by this method has smaller width between the bit lines 106 compared with a node contact formed from a vertical-sidewall opening, in order to prevent the node contact from making contact with the bit lines 106. However the width reduction is not great, and thus a wider reserved tolerance window cannot be further provided. Device shorts caused by electrical connection between the conductive plug 114 of the node contact and the bit line 106 still occur.